(1) Field of the Invention
The invention relates to the general field of thin film transistors, more particularly to improving performance and decreasing manufacturing costs.
(2) Description of the Prior Art
Thin film transistors. (TFTS) have come into widespread use in, among other applications, liquid crystal displays. (LCDs). Most commonly they are fabricated by first laying down a gate electrode on an insulating substrate, then a layer of gate insulation, then a layer of undoped amorphous silicon and then a heavily doped layer of silicon (usually N+) over the preceding silicon layer.
Parasitic capacitances can appear in such a structure in unpredictable ways because of misalignment between source and drain. Additional tolerances must be allowed in the mask design to avoid possible non-contact problems and this can also introduce undesired parasitic capacitances.
An example of a TFT structure, typical of the early prior art, is shown in schematic cross-section in FIG. 1. Gate electrode 2 has been formed on one surface of insulating substrate 1 and then overcoated with gate insulation layer 3 followed by amorphous silicon layer 21 and heavily doped (usually N+) layer of amorphous silicon 22. Layers 21 and 22 were then photolithographically shaped, following which metal layer 24 was deposited over the structure. Conventional photolithography was then again used to partially remove layers 24 and 22 to form gap 25.
In addition to the misalignment and excess overlap problems already discussed, this method has the additional disadvantage that, if underetching occurs during the removal of layer 22, when gap 25 is forming, a certain amount of N+layer 22 will be left on the surface of amorphous silicon layer 21, shorting it out, while, if overetching occurs, the thickness of layer 21 will be less than intended and performance of the device will be degraded. These problems have been partially solved in the prior art through the development of self-aligning techniques, an example of which we will discuss below.
An additional problem associated with the design shown in FIG. 1 is that it is usually difficult to form a low resistance contact between undoped silicon layer 21 and doped silicon layer 22. The latter acts essentially as a metallic contact so that a Schottky barrier is formed between it and the underlying undoped silicon. This problem has been dealt with in the prior art through use of the coplanar structure that we will describe below.
Yet another problem associated with designs such as those of FIG. 1 was their use of amorphous silicon as the active material in the gate region, amorphous silicon having relatively high resistivity even when a conducting channel has been formed on its surface as a result of applying a gate voltage. This problem has been dealt with in the prior art by causing the amorphous silicon to crystallize into polysilicon. This is accomplished by heating the amorphous silicon for a short time at a temperature of at least 600.degree. C. Such a high temperature cannot be applied to an entire structure (such as a LCD) without damaging other parts of it so methods for applying heat very locally for short periods of time (generally several tens of nanoseconds) have been developed. In particular, laser annealing is now widely used for this purpose.
It has been claimed in the prior art by Zhang et al. (U.S. Pat. No. 5,488,000 January 1996) that laser annealing is unreliable primarily because, as the laser is scanned over the areas to be heated, its intensity fluctuates so that uniform results are not obtained. To overcome this problem they teach coating the amorphous silicon with a nucleating layer (for example nickel), prior to crystallization. This allows crystallization to occur at a somewhat lower temperature. We have not found it necessary to use this approach for the method of the present invention.
We now describe a typical prior art method for the manufacture of a TFT that is self-aligned, electrically coplanar (source, drain, and channel lie in the same plane), and uses polysilicon. For more details on the coplanar process and structure, see, for example, Wu (U.S. Pat. No. 5,173,753 December 1992).
Referring now to FIG. 2, the process of the prior art begins with a layer of undoped amorphous silicon 221 that has been deposited onto dielectric substrate 1. Said layer is rapidly and locally annealed by the application of laser beam 29 which causes it to crystallize into polysilicon.
Then, as illustrated in FIG. 3, oxide layer 33 is deposited over layer 221, a metal layer of, for example, chromium is deposited over 33 and then patterned and etched to form gate 35. The structure is then subjected to a high energy dopant ion implantation process 39 which causes dopant to penetrate layer 33 and settle in layer 32, except where they are blocked by gate 35. Thus, after an annealing step, regions 32 become heavily doped polysilicon while region 30 remains undoped and is exactly aligned with gate 39.
The completed structure is as shown in FIG. 4. Dielectric layer 42, usually silicon oxide, is deposited over layer 33. Via holes are then etched through layer 42 down to the level of source/drain regions 32 and filled with conductive plugs 44 which are, in turn, connected to other parts of the circuit (not shown). Finally, passivation layer 43, usually silicon nitride, is deposited over the entire structure.
There are several limitations associated with the prior art process just described. Since the ions that are used to dope the silicon layer must first pass through the gate oxide layer (33) they must have high energy and the introduction of significant radiation damage is unavoidable. Removal of this radiation means higher anneal temperature and/or longer anneal time. Furthermore, in this process there are two separate anneals--one to crystallize the silicon and one to activate the dopant (and remove radiation damage).
Silicon is relatively transparent to near-ultraviolet light, becoming more transparent as the wavelength increases. For example, at a wavelength of about 3300 Angstroms, a layer of silicon about 500 Angstroms thick will reduce the intensity of the light that has passed through it by a factor of about 12, whereas at a wavelength of about 4360 Angstroms, a layer of silicon about 2,000 Angstrom units thick will reduce the intensity of the light that has passed through it by a factor of about 2.7. The present invention takes advantage of this silicon transparency and, in this regard, bears some similarity to pending application ERSO-84-0061.
An example of how this property has been used is shown in FIG. 5. A self-aligned TFT is formed by exposing a layer of positive photoresist to ultraviolet (or near-ultraviolet) light that has been directed to it from the underside of transparent substrate 11. In this manner, the light must pass preformed gate 2 on its way to the photoresist so gate 2 acts as an optical mask. The light must also pass through oxide layer 3 and silicon layer 54 before reaching the photoresist. After development of the photoresist, mask 51 is formed and serves to keep low energy dopant ions from ion stream 52 away from those parts of silicon layer 54 that are directly above gate 2.
In a variation of this process, as shown in FIG. 6, photoresist mask 51 is formed through backside illumination, as before, but instead of doping parts of silicon layer 54 through ion implantation, a layer of heavily doped amorphous silicon 64 is deposited over the structure to make contact with only the parts not covered with photoresist. Opening 65 is then made in layer 64, careful alignment not being necessary as long as said opening underlaps gate 2 and exposes a sufficient amount of mask 51 to allow its easy removal. As part of this removal, any parts of layer 64 that overlap gate 2 are then also removed.